A CMOS 50 MHz CISC superscalar microprocessor

Describes a CISC superscalar microprocessor. It executes 126 instructions with 14 addressing modes, which include floating-point processing fully compatible with the ANSI/IEEE 754-1985 standard. A 64-entry branch-always target buffer (BTB) enables O-cycle branching. An 8-entry return buffer (RB) reduces execution cycles of returns from a subroutine. The processor incorporates 8-kB instruction and operand physical caches (IC and OC), 64-entry instruction and operand translation look-aside buffers (ITLB and OTLB), and a 4-entry store buffer (SB). We focus on two problems particular to adopting a superscalar architecture with a variable-length CISC instruction set. These are: 1) how to dispatch two variable-length instructions per cycle; 2) how to implement complicated operation instructions.