Title :
A 3.3-V analog front-end chip for HomePNA applications
Author :
Jaeyoung Shin; Joongho Choi; Jinup Lim; Sungwon Noh; Namil Baek; Jong-Hyeong Lee
Author_Institution :
Dept. of Electr. Eng., Univ. of Seoul, South Korea
fDate :
6/23/1905 12:00:00 AM
Abstract :
In this paper, we designed the analog front-end chip for HomePNA (Home Phoneline Networking Alliance) physical layer applications. The chip mainly consists of the transmitter (Tx) path and receiver (Rx) path. The transmitter path includes the pulse generation block, Tx filter, programmable gain amplifier, and line driver. The receiver path includes the input buffer, automatic gain control amplifier, Rx filter, and slicing circuit with variable threshold level. The chip is fabricated in a 0.35-/spl mu/m CMOS technology and consumes power dissipation of 150 mW at a 3.3-V supply voltage.
Keywords :
"Transmitters","Filters","Pulse amplifiers","CMOS technology","Physical layer","Pulse generation","Driver circuits","Gain control","Power dissipation","Voltage"
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922333
