A hardware efficient direct digital frequency synthesizer

In this paper, a hardware efficient direct digital frequency synthesizer (DDFS) implementation is presented. To decrease the DDFS hardware requirements, we minimized the size of the lookup table and the other logic parts. The proposed ROM compression algorithm gives a high compression ratio of 236:1. It requires an adder/subtractor and a multiplier. The hardware is further reduced by replacing the standard multiplier with a truncated multiplier. Compared with the previously presented solutions, the proposed DDFS has higher hardware efficiency with equal spurious performance. The synthesizer generates 12-bit sine and cosine waveforms with -84.3 dBc spectral purity, 0.37 Hz frequency resolution, and maximum clock frequency of 100 MHz.