• DocumentCode
    3784054
  • Title

    A new latch-based threshold logic family

  • Author

    M. Padure;S. Cotofana;C. Dan;M. Bodea;S. Vassiliadis

  • Author_Institution
    Politehnica Univ. of Bucharest, Romania
  • Volume
    2
  • fYear
    2001
  • fDate
    6/23/1905 12:00:00 AM
  • Firstpage
    531
  • Abstract
    This paper presents a new low-power threshold logic family with self lock-out property. The simulated results have shown that, the proposed threshold logic dissipates between 10% and 79% less power and between 57% and 71% less energy, at V/sub DD/=5 V, when compared with previous similar threshold logic families. Moreover, at V/sub DD/=3.3 V, it has between 12% and 48% less energy and between 34% and 60% less dissipated power in the worst case.
  • Keywords
    "Boolean functions","Logic devices","Energy consumption","CMOS logic circuits","CMOS technology","Inverters","Switches","Postal services","Digital integrated circuits","Input variables"
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Conference, 2001. CAS 2001 Proceedings. International
  • Print_ISBN
    0-7803-6666-2
  • Type

    conf

  • DOI
    10.1109/SMICND.2001.967522
  • Filename
    967522