DocumentCode :
3784236
Title :
An improved digital quadrature frequency down-converter architecture
Author :
F. Curticapean;J. Niittylahti
Author_Institution :
Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
Volume :
2
fYear :
2001
fDate :
6/23/1905 12:00:00 AM
Firstpage :
1318
Abstract :
This paper describes an improved digital quadrature frequency downconverter architecture. The presented architecture implements the quadrature frequency downconversion as two successive angle rotations. First, a coarse angle rotation is performed by using a modified, low-latency CORDIC algorithm. Then, a fine angle rotation based on a simple trigonometric approximation is realized. Compared with solutions based on the conventional CORDIC algorithm, our architecture offers reduced tuning latency and smaller hardware cost. The use of the presented architecture is especially attractive for frequency agile communication systems.
Keywords :
"Computer architecture","Tuning","Hardware","Frequency conversion","Delay","Digital-to-frequency converters","Iterative algorithms","Costs","Receivers","Frequency synthesizers"
Publisher :
ieee
Conference_Titel :
Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on
ISSN :
1058-6393
Print_ISBN :
0-7803-7147-X
Type :
conf
DOI :
10.1109/ACSSC.2001.987704
Filename :
987704
Link To Document :
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