On test and characterization of analog linear time-invariant circuits using neural networks

Author

Guo, Zhen ; Zhang, Xi Min ; Savir, Jacob ; Shi, Yun-Qing

Author_Institution

Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA

fYear

2001

fDate

2001

Firstpage

338

Lastpage

343

Abstract

Testing and characterization of analog circuits is a very important task in the VLSI manufacturing process. However, no efficient methodology exists on how to effectively model and characterize the various faults, and even how to detect their existence. Neural networks have been successfully applied to various pattern recognition problems. In this paper, the amplitude and temporal characteristics of the good circuit response are used to train a neural network, so that it is able to distinguish between different faulty circuit responses. A Time-Delay Neural Network (TDNN) is proposed as a possible vehicle for performing the test and diagnosis

Keywords

VLSI; analogue integrated circuits; electronic engineering computing; fault location; integrated circuit testing; mixed analogue-digital integrated circuits; neural nets; pattern classification; production testing; ASIC; VLSI manufacturing process; amplitude characteristics; analog circuit characterisation; analog circuit testing; analog linear time-invariant circuits; circuit faults; faulty circuit responses; mixed-signal ICs; multi-dimensional curve classification; neural network training; pattern recognition; sequence classification problem; temporal characteristics; time-delay neural network; Analog circuits; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Manufacturing processes; Neural networks; Pattern recognition; Vehicles; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2001. Proceedings. 10th Asian

Conference_Location

Kyoto

ISSN

1081-7735

Print_ISBN

0-7695-1378-6

Type

conf

DOI

10.1109/ATS.2001.990306

Filename

990306