DocumentCode
3785472
Title
Thermal limitations of InP HBTs in 80- and 160-gb ICs
Author
I. Harrison;M. Dahlstrom;S. Krishnan;Z. Griffith;Y.M. Kim;M.J.W. Rodwell
Author_Institution
Dept. of Electr. & Electron. Eng., Univ. of California, Santa Barbara, CA, USA
Volume
51
Issue
4
fYear
2004
Firstpage
529
Lastpage
534
Abstract
Bipolar transistor scaling laws indicate that the dissipated power per unit collector-junction area increases in proportion to the square of the transistor bandwidth, increasing to /spl sim/10/sup 6/ W/cm/sup 2/ for InP heterojunction bipolar transistors (HBTs) designed for 160 Gb/s operation. A verified three-dimensional finite-element thermal model has been used to analyze the thermal resistance of InP in the context of 80 and 160 Gb/sup -1/ integrated circuits. The simulations show that the maximum temperature in the device can be significantly higher than the experimentally determined base-emitter junction temperature. Devices suitable for 160-Gb/s circuits will be thermally possible if the InGaAs etch-stop or contacting layer is removed from the subcollector.
Keywords
"Heterojunction bipolar transistors","Indium compounds","Phosphorus compounds","Finite element methods","Integrated circuit modeling"
Journal_Title
IEEE Transactions on Electron Devices
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2004.824686
Filename
1275635
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