DocumentCode :
378549
Title :
A high-speed dynamic instruction scheduling scheme for supersealar processors
Author :
Goshima, Masahiro ; Nishino, Kengo ; Nakashima, Yasuhiko ; Mori, Shin-ichiro ; Kitamura, Toshiaki ; Tomita, Shinji
Author_Institution :
Kyoto University
fYear :
2001
fDate :
1-5 Dec. 2001
Firstpage :
225
Lastpage :
236
Keywords :
Broadcasting; CADCAM; CMOS logic circuits; Clocks; Computer aided manufacturing; Degradation; Delay; Dynamic scheduling; Processor scheduling; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microarchitecture, 2001. MICRO-34. Proceedings. 34th ACM/IEEE International Symposium on
ISSN :
1072-4451
Print_ISBN :
0-7965-1369-7
Type :
conf
DOI :
10.1109/MICRO.2001.991121
Filename :
991121
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=378549
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