A 600 MHz VLIW DSP

Author

Agarwala, S. ; Koeppen, P. ; Anderson, T. ; Hill, A. ; Ales, M. ; Damodaran, R. ; Nardini, L. ; Wiley, P. ; Mullinnix, S. ; Leach, J. ; Lell, A. ; Gill, M. ; Golston, J. ; Hoyle, D. ; Rajagopal, A. ; Chachad, A. ; Agarwala, M. ; Castille, R. ; Common, N.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

56

Abstract

A 600 MHz VLIW DSP, which implements the C64x VelociTI.2/spl trade/ architecture delivers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply accumulates at 0.3 mW/MMAC (16 b). The chip has 64 M transistors and dissipates 718 mW at 600 MHz and 1.2 V, and 200 mW at 300 MHz and 0.9 V. It has an 8-way VLIW DSP core, a 2-level memory system, and 2.4 GB/s I/O bandwidth. The DSP chip is implemented in 0.13 μm CMOS technology with 6-layer copper metalization.

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; high-speed integrated circuits; parallel architectures; 0.13 micron; 0.9 to 1.2 V; 16 bit; 200 mW to 718 W; 300 to 600 MHz; 4800 MIPS; 8 bit; C64x VelociTI.2 architecture; CMOS DSP chip; CMOS technology; Cu; data caches; eight-way VLIW DSP core; enhanced DMA controller; enhanced direct memory access controller; high-performance DSP applications; level-2 memory controller; six-layer Cu metalization; two-level memory system architecture; Acceleration; CMOS technology; Decoding; Digital signal processing; Digital signal processing chips; Instruments; Pipelines; Random access memory; Systolic arrays; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.992936

Filename

992936