A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology

Author

Landman, P. ; Ah-Lyan Yee ; Gu, R. ; Parthasarathy, B. ; Gupta, V. ; Ramaswamy, S. ; Dyson, L. ; Bosshart, P. ; Reynolds, J. ; Frannhagen, M. ; Fremrot, P. ; Johansson, S. ; Lewis, K. ; Lee, W.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

72

Abstract

A backplane interconnect ASIC with 62 Gb/s full-duplex aggregate throughput uses 3.1 Gb/s serial link technology organized as 20 bidirectional channels to realize bandwidth. The chip operates with <5/spl times/10/sup 17/ aggregate BER and is fabricated in a 0.18 /spl mu/m CMOS technology, dissipating 9 W in a 768-pin flipchip BGA package.

Keywords

CMOS integrated circuits; application specific integrated circuits; ball grid arrays; flip-chip devices; integrated circuit interconnections; integrated circuit packaging; optical communication equipment; optical fibre networks; telecommunication links; CMOS technology; backplane interconnect ASIC; bandwidth; bidirectional channels; chip BER; flipchip BGA package; full-duplex aggregate throughput; intelligent optical networks; power dissipation; serial link technology; serial-link technology; Application specific integrated circuits; Backplanes; CMOS technology; Circuit noise; Clocks; Delay; Integrated circuit interconnections; Jitter; Phase locked loops; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.992944

Filename

992944