Title :
Design of a low-cost integrated 0.25 /spl mu/m CMOS Bluetooth SOC in 16.5 mm/sup 2/ silicon area
Author :
Cheah, J. ; Ee-Hong Kwek ; Eng Chuan Low ; Chee Kwang Quek ; Yong, C. ; Enright, R. ; Hirbawi, J. ; Lee, A. ; Hongyu Xie ; Longyin Wei ; Le Luong ; Jianping Pan ; Shih-Tsung Yang ; Lau, W.F.A. ; Wai-Lim Ngai
Author_Institution :
Transilica Inc., San Diego, CA, USA
Abstract :
A complete 0.25 /spl mu/m CMOS SOC Bluetooth solution adopts a two-die in a single MCM chip packaging approach with minimum product cost as the most important design goal while maintaining competitive power consumption and RF performance.
Keywords :
CMOS integrated circuits; UHF integrated circuits; integrated circuit design; mixed analogue-digital integrated circuits; multichip modules; wireless LAN; 0.25 micron; Bluetooth; CMOS; MCM; RF performance; SOC; chip packaging approach; design goal; power consumption; product cost; two-die chip; Band pass filters; Bluetooth; CMOS technology; Calibration; Costs; Digital filters; Frequency synthesizers; Linearity; Silicon; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992953
