Title :
A 5 GHz CMOS transceiver for IEEE 802.11a wireless LAN
Author :
Su, D. ; Zargari, M. ; Yue, P. ; Rabii, S. ; Weber, D. ; Kaczynski, B. ; Mehta, S. ; Singh, K. ; Mendis, S. ; Wooley, B.
Author_Institution :
Atheros Commun., Sunnyvale, CA, USA
Abstract :
A 5 GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-complaint WLAN using a 0.25 /spl mu/m CMOS technology occupies 22 mm/sup 2/. The IC has 22 dBm maximum transmitted power, 8 dB overall receive-chain noise figure, and -112 dBc/Hz synthesizer phase noise at 1 MHz offset.
Keywords :
CMOS integrated circuits; UHF integrated circuits; field effect MMIC; integrated circuit noise; mixed analogue-digital integrated circuits; phase noise; transceivers; wireless LAN; 0.25 micron; 5 GHz; 8 dB; CMOS; IEEE 802.11a; RF circuits; WLAN; analog circuits; receive-chain noise figure; synthesizer phase noise; transceiver; transmitted power; wireless LAN; Analog circuits; CMOS analog integrated circuits; CMOS technology; Integrated circuit noise; Integrated circuit synthesis; Noise figure; Radio frequency; Synthesizers; Transceivers; Wireless LAN;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992954
