Title :
A 44 mm/sup 2/ 4-bank 8-word page read 64 Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller
Author :
Tanzawa, T. ; Umezawa, A. ; Taura, T. ; Shiga, H. ; Hara, T. ; Takano, Y. ; Miyaba, T. ; Tokiwa, N. ; Watanabe, K. ; Watanabe, H. ; Masuda, K. ; Naruke, K. ; Kato, H. ; Atsumi, S.
Author_Institution :
Toshiba Corp., Yokohama, Japan
Abstract :
Combining a negative-gate channel-erasing NOR flash memory technology with an aggressively-scaled NAND flash process technology results in a 64 Mb NOR flash memory with 0.27 /spl mu/m/sup 2/ cell and 44 mm/sup 2/ chip. The flash memory provides 4 independent banks for flexible dual operation and unique block redundancy for yield.
Keywords :
CMOS memory circuits; NOR circuits; flash memories; integrated circuit yield; memory architecture; redundancy; 64 Mbit; CMOS; aggressively-scaled NAND flash process; flexible block redundancy; flexible dual operation; negative-gate channel-erasing NOR flash memory; page read; word-line voltage controller; yield; Bandwidth; Decoding; Flash memory; Microelectronics; Solid state circuits; Voltage control;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992959
