DocumentCode
378804
Title
A 125 mm/sup 2/ 1Gb NAND flash memory with 10 MB/s program throughput
Author
Nakamura, H. ; Imamiya, K. ; Himeno, T. ; Yamamura, T. ; Ikehashi, T. ; Takeuchi, K. ; Kanda, K. ; Hosono, K. ; Futatsuyama, T. ; Kawai, K. ; Shirota, R. ; Arai, N. ; Arai, F. ; Hatakeyama, K. ; Hazama, H. ; Saito, M. ; Meguro, H. ; Conley, K. ; Quader, K
Author_Institution
Toshiba Corp., Kanagawa, Japan
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
106
Abstract
A 125 mm/sup 2/ 1Gb NAND flash uses 0.13 /spl mu/m CMOS. The cell is 0.077 /spl mu/m/sup 2/. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.
Keywords
CMOS memory circuits; NAND circuits; flash memories; memory architecture; 0.13 micron; 1 Gbit; 10 MB/s; CMOS; NAND flash memory; chip architecture; chip size; garbage collection; on-chip page copy function; program throughput; CMOS technology; Cameras; Cellular phones; Circuits; Costs; Distributed control; Flash memory; Laser sintering; Throughput; Videos;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.992961
Filename
992961
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