An integrated 802.11a baseband and MAC processor

Author

Thomson, J. ; Baas, B. ; Cooper, E.M. ; Gilbert, J.M. ; Hsieh, G. ; Husted, P. ; Lokanathan, A. ; Kuskin, J.S. ; McCracken, D. ; McFarland, B. ; Meng, T.H. ; Nakahira, D. ; Ng, S. ; Rattehalli, M. ; Smith, J.L. ; Subramanian, R. ; Thon, L. ; Yi-Hsiu Wang

Author_Institution

Atheros Commun., Sunnyvale, CA, USA

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

126

Abstract

An 0.25 /spl mu/m CMOS mixed-signal baseband and MAC processor for the IEEE 802.11a WLAN standard in 0.25 /spl mu/m CMOS occupies 6.8/spl times/6.8 mm/sup 2/ and contains 4.0M transistors in a 196-pin BGA package. Power consumption for transmit and receive is 326 mW and 452 mW. Additional data rates up to 108 Mb/s are supported. The MAC is implemented using dedicated control and datapath logic, and includes registers that allow host software to configure and control its operation. This yields an overall design that is compact, power-efficient, and requires no off-chip RAM or program storage, yet is very flexible.

Keywords

CMOS integrated circuits; IEEE standards; OFDM modulation; computer architecture; microprocessor chips; mobile radio; radio receivers; radio transmitters; wireless LAN; 0.25 /spl mu/m CMOS; 0.25 micron; 108 Mbit/s; 326 mW; 452 mW; ADC; BGA package; MAC architecture; MAC processor; WLAN standard; baseband receiver; baseband transmitter; coded OFDM modulation; two-chip set; Baseband; Code standards; Digital filters; Engines; Filtering; Logic; Protocols; Sleep; Transmitters; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.992968

Filename

992968