• DocumentCode
    378813
  • Title

    Jitter optimization based on phase-locked loop design parameters

  • Author

    Mansuri, M. ; Chih-Kong Ken Yang

  • Volume
    1
  • fYear
    2002
  • fDate
    7-7 Feb. 2002
  • Firstpage
    138
  • Abstract
    A tunable PLL allows independent optimization of loop parameters. The effects of varying PLL parameters (damping factor and bandwidth) on timing jitter is derived analytically and verified experimentally.
  • Keywords
    phase locked loops; timing jitter; bandwidth; damping factor; design optimization; timing jitter; tunable phase locked loop; Band pass filters; Bandwidth; Clocks; Colored noise; Design optimization; Equations; Filtering; Phase locked loops; Timing jitter; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Print_ISBN
    0-7803-7335-9
  • Type

    conf

  • DOI
    10.1109/ISSCC.2002.992974
  • Filename
    992974
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=378813