Title :
The clock distribution of the Power4 microprocessor
Author :
Restle, P.J. ; Carter, C.A. ; Eckhardt, J.P. ; Krauter, B.L. ; McCredie, B.D. ; Jenkins, K.A. ; Weger, A.J. ; Mule, A.V.
Author_Institution :
IBM Res., Yorktown Heights, NY, USA
Abstract :
The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.
Keywords :
CMOS digital integrated circuits; VLSI; clocks; digital phase locked loops; high-speed integrated circuits; microprocessor chips; silicon-on-insulator; synchronisation; timing; 1.5 GHz; CMOS process; Power4 microprocessor; SOI-optimized PLL; Si; clock distribution; dual-processor chip; Capacitors; Circuits; Clocks; Delay; Frequency conversion; Hardware; Jitter; Microprocessors; Phase locked loops; Semiconductor device measurement;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992977
