Title :
Memory design using one-transistor gain cell on SOI
Author :
Ohsawa, T. ; Fujita, K. ; Higashi, T. ; Iwata, Y. ; Kajiyama, T. ; Asao, Y. ; Sunouchi, K.
Author_Institution :
Memory Div., Toshiba Corp., Yokohama, Japan
Abstract :
A 512 kb DRAM has a 7F/sup 2/ one-transistor gain cell (F=0.18 /spl mu/m) on SOI. The array driving method makes selective write possible. Basic operation is verified by device simulation and hardware measurement. Simulations show 40 ns access time. Non-destructive readout and Cb/Cs-free signal development improve cell efficiency.
Keywords :
DRAM chips; MOS memory circuits; cellular arrays; circuit simulation; integrated circuit design; integrated circuit measurement; integrated circuit modelling; silicon-on-insulator; 0.18 micron; 40 ns; 512 kbit; DRAM; MOS process; SOI; Si; access time; array driving method; device simulation; hardware measurement; memory design; nondestructive readout; one-transistor gain cell; selective write; Capacitors; Data engineering; Large scale integration; Lead compounds; MOSFETs; Microelectronics; Random access memory; Research and development; Time measurement; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992981
