A hierarchy bitline boost scheme for sub-1.5 V operation and short precharge time on high density FeRAM

Author

Hee-Bok Kang ; Hun-Woo Kye ; Geun-Il Lee ; Je-Hoon Park ; Jun-Hwan Kim ; Seaung-Suk Lee ; Suk-Kyoung Hong ; Young-Jin Park ; Jin-Yong Chung

Author_Institution

Memory R&D Center, Hynix Semicond., Ichon, South Korea

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

158

Abstract

This work develops three concepts: low-voltage operation with boost voltage control of bitline and plateline, reduced bitline capacitance with multiple divided sub cell array, and increased chip performance with write operation sharing both active and precharge time period. A 256 kb test chip with 3.0/spl times/1.0 /spl mu/m/sup 2/ 1T1C memory cells in 0.25 /spl mu/m design roles is expected to achieve 180 ns access and 70 ns precharge at 1.5 V based on internal probing.

Keywords

capacitance; ferroelectric storage; integrated circuit design; integrated circuit measurement; integrated memory circuits; low-power electronics; random-access storage; voltage control; 0.25 micron; 1 micron; 1.5 V; 180 ns; 1T1C memory cells; 256 kbit; 3 micron; 70 ns; active time period; bitline boost voltage control; bitline capacitance; chip performance; design rules; hierarchy bitline boost scheme; high density FeRAM; internal probing; low voltage operation; multiple divided sub cell array; plateline boost voltage control; precharge time; precharge time period; test chip; write operation; Capacitance; Ferroelectric films; Ferroelectric materials; Nonvolatile memory; Polarization; Random access memory; Research and development; Switches; Variable structure systems; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.992984

Filename

992984