A 0.25 /spl mu/m 3.0 V 1T1C 32 Mb nonvolatile ferroelectric RAM with address transition detector (ATD) and current forcing latch sense amplifier (CFLSA) scheme

Author

Mun-Kyu Choi ; Byung-Gil Jeon ; Nakwon Jang ; Byung-Jun Min ; Yoon-Jong Song ; Sung-Yung Lee ; Hyun-Ho Kim ; Dong-Jin Jung ; Heung-Jin Joo ; Kinam Kim

Author_Institution

Samsung Electron., Kiheung, South Korea

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

162

Abstract

A nonvolatile 32 Mb ferroelectric random-access memory with 0.25 /spl mu/m design rules uses ATD control for SRAM applications and a common-plate folded bit-line cell scheme with current forcing latched sense amplifier for low noise level without cell area penalty.

Keywords

SRAM chips; ferroelectric storage; integrated circuit design; integrated circuit measurement; integrated circuit noise; 0.25 micron; 3 V; 32 Mbit; ATD control; SRAM applications; address transition detector; cell area penalty; common-plate folded bit-line cell scheme; current forcing latch sense amplifier scheme; design rules; noise level; nonvolatile ferroelectric RAM; nonvolatile ferroelectric random-access memory; Capacitors; Consumer electronics; Control systems; Ferroelectric films; Ferroelectric materials; Latches; Nonvolatile memory; Operational amplifiers; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.992986

Filename

992986