Title :
A 10b 120MSample/s time-interleaved analog-to-digital converter with digital background calibration
Author :
Jamal, S.M. ; Daihong Fu ; Hurst, P.J. ; Lewis, S.H.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Abstract :
Digital calibration using adaptive signal processing corrects offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10b 120MSample/s pipelined ADC. With background calibration, peak SNDR is 56.8dB and power dissipation is 234mW from 3.3V. Active area is 12.5mm/sup 2/ in 0.35/spl mu/m CMOS.
Keywords :
CMOS integrated circuits; adaptive signal processing; analogue-digital conversion; calibration; low-power electronics; pipeline processing; 0.35 micron; 10 bit; 234 mW; 3.3 V; CMOS; active area; adaptive signal processing; digital background calibration; gain mismatch; offset mismatch; pipelined ADC; power dissipation; sample-time error; time-interleaved analog-to-digital converter; Analog-digital conversion; Calibration; Choppers; Delay; Detectors; Finite impulse response filter; Frequency; Interleaved codes; Phase detection; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992991
