Title :
Cellular supercomputing with system-on-a-chip
Author :
Almasi, G. ; Almasi, G.S. ; Beece, D. ; Bellofatto, R. ; Bhanot, G. ; Bickford, R. ; Blumrich, M. ; Bright, A.A. ; Brunheroto, J. ; Cascaval, C. ; Castanos, J. ; Ceze, L. ; Coteus, P. ; Chatterjee, S. ; Chen, D. ; Chiu, G. ; Cipolla, T.M. ; Crumley, P. ;
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
System-on-a-chip technology allows a level of integration that can be leveraged to develop inexpensive high-performance, low-power computing nodes. When used in aggregate, this approach promises to challenge conventional supercomputer architectures in the high-performance computing arena. Systems under consideration reach into the hundreds of thousand nodes per machine. Architecture for these systems are described.
Keywords :
low-power electronics; parallel architectures; parallel machines; cellular supercomputing; high-performance low-power computing; supercomputer architecture; system-on-a-chip; Application specific integrated circuits; Bandwidth; Computer architecture; Delay; Ethernet networks; Network servers; Routing; Supercomputers; System-on-a-chip; Throughput;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.993003
