Title :
A 3 V /spl Delta//spl Sigma/ receiver with sampling rate enhancement for CDMA baseband processor IC
Author :
Liu, E. ; Chen, M. ; Pan, M.
Author_Institution :
LSI Logic Corp., Milpitas, CA, USA
Abstract :
A 3V /spl Delta//spl Sigma/ CDMA baseband receiver has been designed which has a 4th-order single-loop modulator that enhances the effective sampling rate without increasing the actual rate, achieves 62 dB DR (dynamic range), consumes 22 mW, and occupies 1.3 mm/sup 2/ in 0.25 /spl mu/m CMOS. This receiver is part of an 8 M transistor 10.5/spl times/10.5 mm chip which integrates receiver, transmitter, voice codec, 10 bit ADC and DAC, PLL, 32 kHz oscillator, two DSPs, memory, and ARM.
Keywords :
CMOS integrated circuits; code division multiple access; delta-sigma modulation; digital filters; microprocessor chips; mobile radio; radio receivers; signal sampling; 0.25 micron; 10 bit; 10.5 mm; 22 mW; 3 V; 32 kHz; ADC; ARM; CDMA baseband processor IC; CMOS /spl Delta//spl Sigma/ CDMA baseband receiver; DAC; DSP; PLL; delta sigma modulation; digital filters; dynamic range; effective sampling rate; fourth-order single-loop modulator; integrated memory; oscillators; sampling rate enhancement; transmitters; voice codecs; Baseband; Codecs; Delta modulation; Digital signal processing chips; Dynamic range; Multiaccess communication; Oscillators; Phase locked loops; Sampling methods; Transmitters;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.993018
