A 10 Gb/s CDR/DEMUX with LC delay line VCO in 0.18 /spl mu/m CMOS

Author

Rogers, J.E. ; Long, J.R.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

254

Abstract

A monolithic 10 Gb/s clock/data recovery and 1:2 demultiplexer is implemented in 0.18 /spl mu/m CMOS. The quadrature LC delay line oscillator has 110 MHz tuning range and 60 MHz/V sensitivity to power-supply pulling. The circuit meets SONET OC-192 requirements with 1 ps rms measured jitter. The 1.9/spl times/1.5 mm/sup 2/ IC consumes 285 mW from a 1.8 V supply.

Keywords

CMOS integrated circuits; SONET; delay lines; demultiplexing equipment; integrated circuit measurement; optical fibre networks; optical receivers; synchronisation; voltage-controlled oscillators; 0.18 micron; 1 ps; 1.5 mm; 1.8 V; 1.9 mm; 10 Gbit/s; 285 mW; CDR/DEMUX; CMOS implementation; CMOS technology; LC delay line VCO; SONET OC-192 requirements; monolithic clock/data recovery-demultiplexer circuit; power consumption; power-supply pulling sensitivity; quadrature LC delay line oscillator; rms measured jitter; tuning range; Clocks; Delay lines; Detectors; Frequency; Parasitic capacitance; Phase detection; Phase locked loops; Phase noise; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.993032

Filename

993032