Title :
A 33mW 14b 2.5MSample/s /spl Sigma//spl Delta/ A/D converter in 0.25/spl mu/m digital CMOS
Author :
Reutemann, R. ; Balmelli, P. ; Qiuting Huang
Author_Institution :
Integrated Syst. Lab., Eidgenossische Tech. Hochschule, Zurich, Switzerland
Abstract :
The IC consists of a 5th-order single-loop tri-level /spl Sigma//spl Delta/ modulator and a multistage digital filter. Measured dynamic range is 86dB over 1 MHz bandwidth. With 79dB peak SNDR, the chip consumes 33mW and occupies 1.5mm/sup 2/.
Keywords :
CMOS integrated circuits; digital filters; low-power electronics; sigma-delta modulation; /spl Sigma//spl Delta/ A/D converter; 0.25 micron; 1 MHz; 14 bit; 33 mW; digital CMOS; dynamic range; multistage digital filter; peak SNDR; power consumption; single-loop tri-level /spl Sigma//spl Delta/ modulator; Capacitors; Circuit noise; Digital filters; Digital modulation; Dynamic range; Energy consumption; Finite impulse response filter; Passband; Sampling methods; Stability;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.993059
