DocumentCode
378869
Title
A 0.5/spl mu/m CMOS low-distortion low-power line driver with embedded digital adaptive bias algorithm for integrated ADSL analog front-ends
Author
Ingels, M. ; Bojja, S. ; Wouters, P.
Author_Institution
Alcatel Microelectron., Zaventem, Belgium
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
324
Abstract
A 5V 0.5/spl mu/m CMOS line driver has distortion <-65dB in the ADSL upstream band for a 4V peak-to-peak differential output swing on a 12.5/spl Omega/ load. The quiescent current is controlled digitally with a dedicated algorithm that corrects for offsets and process variations. The driver is integrated in a complete ADSL CPE analog front-end.
Keywords
CMOS analogue integrated circuits; digital subscriber lines; driver circuits; electric distortion; low-power electronics; 0.5 micron; 5 V; CMOS low-distortion low-power line driver; embedded digital adaptive bias algorithm; integrated ADSL CPE analog front-end; peak-to-peak differential output swing; quiescent current; CMOS technology; Current measurement; Digital control; Driver circuits; Energy consumption; Impedance; Low voltage; MOS devices; Microelectronics; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.993063
Filename
993063
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