Title :
Implementation of a third-generation 1.1GHz 64b microprocessor
Author :
Konstadinidis, G. ; Normoyle, K. ; Wong, S. ; Bhutani, S. ; Stuimer, H. ; Johnson, T. ; Smith, A. ; Cheung, D. ; Romano, F. ; Shifeng Yu ; Sung-Hun Oh ; Melamed, V. ; Narayanan, S. ; Bunsey, D. ; Khieu, C. ; Wu, K.J. ; Schmitt, R. ; Dumlao, A. ; Sutera, M
Author_Institution :
Sun Microsystems, Palo Alto, CA, USA
Abstract :
A third-generation 1.1 GHz 64b microprocessor provides 1 MB on-chip L2$, 4GB/s off chip memory bandwidth and a 200MHz JBUS interface that supports 1 to 4 processors. The 90M transistor chip is implemented in a 7-level metal copper 0.13/spl mu/m CMOS process and dissipates 53W at 1.3V and 1.1GHz.
Keywords :
CMOS digital integrated circuits; microprocessor chips; 0.13 micron; 1 MB; 1.1 GHz; 1.3 V; 200 MHz; 4 GB/s; 53 W; 64 bit; CMOS process; Cu; JBUS interface; off-chip memory bandwidth; on-chip L2$; third-generation microprocessor; Bandwidth; Central Processing Unit; Circuits; Clocks; Delay; Error correction codes; Frequency synchronization; Microprocessors; Protection; Sun;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.993070
