Author :
Ohashi, M. ; Hashimoto, T. ; Kuromaru, S.I. ; Matsuo, M. ; Mori-iwa, T. ; Hamada, M. ; Sugisawa, Y. ; Arita, M. ; Tomita, H. ; Hoshino, M. ; Miyajima, H. ; Nakamura, T. ; Ishida, K.I. ; Kimura, T. ; Kohashi, Y. ; Kondo, T. ; Inoue, A. ; Fujimoto, H. ; Wat
Abstract :
A single-chip MPEG-4 video decoder LSI with integrated 896 kb embedded SRAM frame buffer and embedded video display engine consumes 11.1 mW at 27 MHz operation. The chip achieves QCIF 15 Hz H.263 and Simple@L1 decoding capability on a 37.26 mm/sup 2/ die using 0.18 μm 1.5 V quad-metal CMOS technology.
Keywords :
CMOS digital integrated circuits; VLSI; code standards; data compression; decoding; digital signal processing chips; high-speed integrated circuits; video coding; visual communication; 0.18 micron; 1.5 V; 11.1 mW; 27 MHz; H.263 decoding capability; MPEG-4 video decoder LSI; Simple@L1 decoding capability; embedded SRAM frame buffer; embedded video display engine; mobile application; quad-metal CMOS technology; single-chip decoder; Clocks; Decoding; Energy consumption; Engines; Frequency; Large scale integration; MPEG 4 Standard; Noise reduction; Random access memory; Reduced instruction set computing;
