DocumentCode
378884
Title
An MPEG-4 video LSI with an error-resilient codec core based on a fast motion estimation algorithm
Author
Nakayama, H. ; Yoshitake, T. ; Komazaki, H. ; Watanabe, Y. ; Araki, H. ; Morioka, K. ; Li, J. ; Peilin, L. ; Lee, S. ; Kubosawa, H. ; Otobe, Y.
Author_Institution
Fujitsu Labs. Ltd., Kawasaki, Japan
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
368
Abstract
An MPEG-4 video codec core based on a scene-adaptive motion estimation algorithm is integrated into 5.296/spl times/5.296 mm/sup 2/ die using 0.18 /spl mu/m quad-metal technology. The power dissipation during codec operation of the device is 131 mW for QCIF format at 15 frames/s at 13.5 MHz using a 1.5 V supply.
Keywords
CMOS digital integrated circuits; large scale integration; low-power electronics; motion estimation; video codecs; 0.18 micron; 1.5 V; 13.5 MHz; 131 mW; MPEG-4; QCIF format; error-resilient codec core; fast motion estimation algorithm; power dissipation; quad-metal technology; scene-adaptive motion estimation; video LSI; Clocks; Codecs; Decoding; Encoding; Large scale integration; MPEG 4 Standard; Motion estimation; Pipelines; Power dissipation; Resilience;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.993085
Filename
993085
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