An 8-way VLIW embedded multimedia processor built in 7-layer metal 0.11 /spl mu/m CMOS technology

Author

Okano, Hiroshi ; Suga, A. ; Shiota, Takashi ; Takebe, Y. ; Nakamura, Yoshihiko ; Higaki, N. ; Kimura, Hiromitsu ; Miyake, Hirokazu ; Satoh, T. ; Kawasaki, Keisuke ; Sasagawa, R. ; Shibamoto, W. ; Sasaki, Motoharu ; Ando, Nozomu ; Yamana, T. ; Fukushi, I.

Author_Institution

Fujitsu Labs. Ltd., Kanagawa, Japan

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

374

Abstract

A 533 MHz 2.5 W 2132 MIPS 12.8 GOPS 2.1 GFLOPS 8-way VLIW embedded multimedia processor occupies a 7.8/spl times/7.8 mm/sup 2/ die in a 7-layer metal 0.11 /spl mu/m CMOS at 1.2 V. VLIW, SIMD, dynamic branch prediction, non-aligned dual load/store mechanism and a crosstalk-aware design flow contribute to performance.

Keywords

CMOS digital integrated circuits; crosstalk; digital signal processing chips; embedded systems; integrated circuit design; multimedia communication; multimedia computing; parallel architectures; 0.11 micron; 1.2 V; 2.1 GFLOPS; 2.5 W; 2132 MIPS; 533 MHz; 7.8 mm; SIMD; VLIW embedded multimedia processor; crosstalk-aware design flow; dynamic branch prediction; nonaligned dual load/store mechanism; processor performance; seven-layer metal CMOS technology; CMOS process; CMOS technology; Crosstalk; Decoding; Delay effects; Delay estimation; Frequency; History; Repeaters; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.993088

Filename

993088