Title :
A fully-integrated GPS receiver front-end with 40 mW power consumption
Author :
Steyaert, M. ; Coppejans, P. ; De Cock, W. ; Leroux, P. ; Vancorenland, P.
Author_Institution :
Katholieke Univ., Leuven, Belgium
Abstract :
A 0.25 /spl mu/m CMOS quadrature complex bandpass low-IF GPS receiver includes an LNA, PLL, mixer and a continuous-time /spl Delta//spl Sigma/ ADC. The chip has -130 dBm input sensitivity, 62 dB DR, and -32 dB IMRR, while consuming 40 mW from 2 V supply. The chip is 9 mm/sup 2/.
Keywords :
CMOS integrated circuits; Global Positioning System; UHF integrated circuits; low-power electronics; radio receivers; 0.25 micron; 2 V; 40 mW; CMOS; DR; GPS receiver front-end; IMRR; LNA; PLL; continuous-time /spl Delta//spl Sigma/ ADC; input sensitivity; mixer; power consumption; quadrature complex bandpass low-IF receiver; Band pass filters; Energy consumption; GSM; Global Positioning System; Low-noise amplifiers; Noise figure; Noise shaping; Phase locked loops; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.993099
