Title :
A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS
Author :
Vangal, S. ; Borkar, N. ; Seligman, E. ; Govindarajulu, V. ; Erraguntla, V. ; Wilson, H. ; Pangal, A. ; Veeramachaneni, V. ; Anders, M. ; Tschanz, J. ; Ye, Y. ; Somasekhar, D. ; Bloechel, B. ; Dermer, G. ; Krishnamurthy, R. ; Narendra, S. ; Stan, M. ; Tho
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
A 32 b integer execution core implements 12 instructions. Circuit and body bias techniques together increase the core clock frequency to 5 GHz. In a 130 nm six-metal dual-V/sub T/ CMOS process, the 2.3 mm/sup 2/ prototype contains 160 k transistors, with RF-ALU units dissipating 515 mW at 1.6 V.
Keywords :
CMOS logic circuits; adders; buffer circuits; digital arithmetic; leakage currents; 1.6 V; 130 nm; 25 GHz; 32 bit; 5 GHz; 515 mW; RF-ALU units; body bias techniques; core clock frequency; dual-V/sub T/ CMOS; integer-execution core; six-metal CMOS process; Adders; CMOS process; CMOS technology; Centralized control; Circuits; Delay; MOS devices; Power measurement; Radio frequency; Sleep;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.993107
