DocumentCode
378899
Title
A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions
Author
Rogenmoser, R. ; O´Donnell, L. ; Nishimoto, S.
Author_Institution
Broadcom, Santa Clara, CA, USA
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
414
Abstract
A floating-point coprocessor, part of a MIPS64 dual-processor SOC, consists of a 32/spl times/64b register file and two pipes each with a multiplier, an adder, and a fast 3D approximation unit. It operates up to 1 GHz at 1.3 W, measures 4.74 mm/sup 2/ in 0.13 /spl mu/m CMOS, and has peak performance of 8 GFlops per CPU and 16 GFlops on the dual-processor SOC.
Keywords
CMOS digital integrated circuits; coprocessors; floating point arithmetic; parallel architectures; pipeline arithmetic; 0.13 micron; 1 GHz; 1.3 W; 3D approximation unit; 3D functions; CMOS; MIPS64 dual-processor SOC; SIMD architecture; dual-issue floating-point coprocessor; pipes; register file; Adders; CMOS technology; Central Processing Unit; Circuits; Coprocessors; Delay; Ethernet networks; Power dissipation; Registers; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.993108
Filename
993108
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