Title :
The high-bandwidth 256 kB 2nd level cache on an Itanium microprocessor
Author :
Riedlinger, R. ; Grutkowski, T.
Author_Institution :
Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
This paper describes the second level 256 kB unified cache incorporated into the next generation of the Itanium/spl trade/ processor family code named McKinley. The paper describes the datapath structures that provide a non-blocking, out-of-order interface to the processor core achieving a minimum 5-cycle latency with a standalone bandwidth of 72 GB/s.
Keywords :
cache storage; microprocessor chips; 256 kB; 2nd level cache; Itanium microprocessor; McKinley; datapath structures; high-bandwidth cache; nonblocking out-of-order interface; Bandwidth; Circuits; Delay; Error correction; Error correction codes; Microprocessors; Out of order; Pipelines; Robustness; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.993110
