A lithographic process for integrated organic field-effect transistors

This paper reports a photolithographic process for fabricating organic field-effect transistors which provides two layers of metal with arbitrary via placement, and optionally allows for subtractive lithographic patterning of the transistor active layer. The demonstrated pentacene transistors have a field-effect mobility of 0.1/spl plusmn/0.05 cm/sup 2//(V/spl middot/s). Parylene-C is used both as the gate dielectric and an encapsulation layer which allows for subtractive lithographic patterning. Also demonstrated is a PMOS inverter without level shifting circuitry and level-restoring V/sub High/ and V/sub Low/. This work demonstrates a high definition, multilayer, integrated photolithographic process which creates organic field effect transistors suitable for use in integrated circuit applications such as a display backplanes.