DocumentCode :
379137
Title :
Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization
Author :
Cheng, Kuo-Hsing ; Cheng, Shun-Wen
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan
fYear :
2002
fDate :
2002
Firstpage :
155
Lastpage :
159
Abstract :
Comparing CMOS logic with pass-transistor logic, a question was raised in the minds of the authors: "does any rule exist that contains all good?" This paper reveals novel logic synthesis and optimization procedures for full swing arbitrary logic function. The novel procedures are called prioritized prime implicant patterns puzzle (PPIPP). Following the proposed procedures, we can get a new hybrid high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and is suitable for low supply voltage. It has full swing signal in all nodes and high robustness against transistor downsizing and voltage scaling
Keywords :
CMOS logic circuits; VLSI; circuit CAD; circuit optimisation; logic CAD; low-power electronics; CMOS logic; VLSI; area efficiency; full swing arbitrary logic function; logic optimization; logic synthesis; low supply voltage; pass-transistor logic; power consumption; power-delay product; prioritized prime implicant patterns puzzle; robustness; transistor downsizing; voltage scaling; CMOS logic circuits; Circuit synthesis; Energy consumption; Logic circuits; Logic design; Logic functions; Low voltage; MOSFETs; Robustness; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
Type :
conf
DOI :
10.1109/ASPDAC.2002.994909
Filename :
994909
Link To Document :
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