Title :
Net clustering based macrocell placement
Author :
Alupoaei, Stelian ; Katkoori, Srinivas
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
Given an RTL (Register-Transfer-Level) netlist, a net dependency graph with weighted edges is built. Each node in the graph represents a net and an edge exists between two nodes if the two nets represented by the nodes share one or more macrocells. Clusters of nets are then formed by clique partitioning. A net cluster level floorplan is derived by simulated annealing to define the regions where the nets in each cluster must be routed. The macrocell placement is formulated as a force-directed problem where the terminals of a net are free to move under the influence of forces in the quest for optimal length of the net. A new type of rejection force is introduced in order to obtain a feasible placement. In comparison with the placements generated by CADENCE Silicon Ensemble, we obtained an average total wire length reduction of 22.8% and an average longest wire length reduction of 33% with an average area penalty of only 1.1%
Keywords :
VLSI; cellular arrays; circuit layout CAD; circuit optimisation; graph theory; high level synthesis; integrated circuit interconnections; integrated circuit layout; logic arrays; RTL macrocell placement; RTL netlist; clique partitioning; force-directed problem; interconnect model; net cluster level floorplan; net clustering based macrocell placement; net dependency graph; register-transfer-level netlist; rejection force; simulated annealing; weighted edges; wire length reduction; Computer science; Costs; Delay; Macrocell networks; Pins; Quadratic programming; Silicon; Simulated annealing; Topology; Wire;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.994954
