Title :
Probabilistic analysis of rectilinear Steiner trees
Author_Institution :
Dept. of Electr. & Comput. Eng., Windsor Univ., Ont., Canada
Abstract :
The Steiner tree is a fundamental concept in automatic interconnect optimization for VLSI design. We present a probabilistic analysis method for constructing rectilinear Steiner trees. The best solution in a statistical sense is obtained for any given set of N points. Experiments show that our results are better than those by previous techniques and are very close to the optima
Keywords :
VLSI; circuit layout CAD; circuit optimisation; integrated circuit interconnections; integrated circuit layout; network routing; network topology; probability; statistical analysis; trees (mathematics); Steiner tree; VLSI design; VLSI interconnect design; automatic interconnect optimization; probabilistic analysis; rectilinear Steiner trees; signal nets; topology construction; Costs; Design optimization; Joining processes; Pins; Probability; Signal design; Topology; Tree data structures; Very large scale integration; Wire;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.994967
