Title :
Strategies for improving data locality in embedded applications
Author :
Crosbie, N.E. ; Kandemir, M. ; Kolcu, I. ; Ramanujam, J. ; Choudhary, A.
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
This paper introduces a dynamic layout optimization strategy to minimize the number of cycles spent in memory accesses in a cache-based memory environment. In this approach, a given multi-dimensional array may have different memory layouts in different segments of the same application if doing so improves data locality (cache behavior) beyond the static approaches that fix memory layouts at specific forms at compile-time. An important characteristic of this strategy is that different memory layouts that a given array will assume at run-time are determined statically at compile-time; however the layout modifications (transformations), themselves, occur dynamically during the course of execution. To test the effectiveness of our strategy, we used it in optimizing several array-dominated applications. Our preliminary results on an embedded MIPS processor core show that this dynamic strategy is very successful and outperforms previous approaches based on loop transformations, data transformations, or integrated loop/data transformations
Keywords :
cache storage; embedded systems; microprocessor chips; optimising compilers; storage management; cache memory; data locality; dynamic layout optimization; embedded MIPS processor; multi-dimensional array; optimizing compiler; Cache memory; Design optimization; Dynamic compiler; Engineering profession; Flow graphs; Optimizing compilers; Random access memory; Runtime; Testing; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.995007