A high-speed architecture for CMA blind equalizer

We propose an architecture for pipelined FIR ADF based on the CMA (constant modulus algorithm), which is a kind of blind equalizer. One of the features of proposed architecture, is its latency, which is independent of the number of taps of coefficients, and whose value is always fixed to a single clocking period. As of the critical path, the proposed method has a shorter path in comparison with conventional CMA using the direct form FIR ADF. Thus, an improvement in the processing speed and a lower power consumption can be attained. Some computer simulation are shown to verify the effectiveness of the proposed method