Abstract :
In this paper drawbacks of the three-state data compressor in the form of the unit decoder 3/2—JK flip-flop are described. The main results of the paper are the algebraic operation model and the description of detection capability of a new three-state data stream compressor consisting of decoder 3/2 and a two-input shift register TISR. In particular, the properties of the unit decoder 3/2—TISR in detecting faults of the s-a-0, s- a-1, and s-a-HZ type are discussed. In this paper important aspects of the application of the new compressor are given. An example of the new compressor´s performance scheme is also described. An additional result of this paper is the description of the operation model and the detection capability of the multiinput shift register MISR in which the most significant bit and other selected flip-flop output signals are fed back to the least significant bit positions via Exclusive-OR gates outside the flip-flops.
