DocumentCode
379557
Title
A 2-stage matching scheduler for a VOQ packet switch architecture
Author
Jiang, Ying ; Hamdi, Mounir
Author_Institution
Suntek Technol. Co., Ltd., Beijing, China
Volume
4
fYear
2002
fDate
2002
Firstpage
2105
Abstract
Virtual output queuing (VOQ) is a practical and high-performance packet switch architecture. There are many simple iterative arbitration algorithms proposed for the VOQ architecture. These algorithms either employ a 3-phase or a 2-phase handshaking scheme between the switch inputs and outputs. It has been shown that neither scheme can outperform the other in all traffic patterns. As a result, we propose a 2-stage matching algorithm that combines the benefit of both schemes, and also achieves the best desynchronization of arbiter pointers during their scheduling. We demonstrate that this new algorithm outperforms all the other iterative algorithms considered under various traffic models. We also propose a possible hardware implementation method of the algorithm.
Keywords
iterative methods; packet switching; queueing theory; scheduling; synchronisation; telecommunication traffic; VOQ; arbiter pointers; desynchronization; hardware implementation; high-performance architecture; iterative arbitration algorithms; packet switch architecture; scheduling; traffic models; two-stage matching scheduler; virtual output queuing; Computer architecture; Computer science; Hardware; Iterative algorithms; Packet switching; Processor scheduling; Scheduling algorithm; Switches; Throughput; Traffic control;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, 2002. ICC 2002. IEEE International Conference on
Print_ISBN
0-7803-7400-2
Type
conf
DOI
10.1109/ICC.2002.997219
Filename
997219
Link To Document