ASIC test sequence minimisation by built-in testability in logic surrounding embedded binary asynchronous counters

The parallel/serial test procedure for application-specific integrated circuit (ASIC) logic surrounding embedded asynchronous counters is proposed, which increases counter controllability and observability and reduces test sequence length. Optimisation of counter partitioning and test sequence generation is carried out with the CAD program COUNTESS. For optimal partitioning COUNTESS calculates both the test hardware overhead and the minimum number of test cycles.