A simple and effective scheduling mechanism using minimized cycle round robin

In this paper, we first present a simple scheduling scheme called minimized cycle round robin (MCRR) for packet and cell switched networks. We demonstrate that MCRR exhibits optimal worst-case latency property in a certain class of weighted round robin (WRR) approaches which are currently used for packet (cell) scheduling in high-speed networks, such as ATM networks. We further present a hierarchical MCRR (HMCRR) mechanism to maximize the efficacy of MCRR in practice and be scalable to large number of connections. HMCRR can significantly improve router/switch scheduling latency and hence the delay and delay jitter performance, while keeping the simplicity of WRR based scheduling disciplines.