A Note on the Basic Block Diagrams of Finite Automata from the Engineering Point of View

The use of a parallel multiplier for performing high-speed binary division requires that an algorithm be devised that obtains the quotient by means of multiplications and additions. Furthermore, its hardware implementation must be as simple and as fast as possible. A suitable algorithm, which applies to a first approximation to the reciprocal of the divisor, has already been proposed[1]. A similar algorithm is presented in this paper. The comparison between the two methods for equal numbers of multiplications shows that the latter is more accurate. Conversely, a given accuracy can often be obtained with a higher speed. The generation of a piecewise-linear initial approximation is also discussed.