EAC: a compiler framework for high-level energy estimation and optimization

Author

Kadayif, I. ; Kandemir, M. ; Vijaykrishnan, N. ; Irwin, M.J. ; Sivasubramaniam, A.

Author_Institution

Microsystems Design Lab, Pennsylvania State Univ., University Park, PA, USA

fYear

2002

fDate

2002

Firstpage

436

Lastpage

442

Abstract

This paper presents a novel Energy-Aware Compilation (EAC) framework that can estimate and optimize energy consumption of a given code taking as input the architectural and technological parameters, energy models, and energy/performance constraints,. The framework has been validated using a cycle-accurate architectural-level energy simulator and found to be within 6% error margin while providing significant estimation speedup. The estimation speed of EAC is the key to the number of optimization alternatives that can be explored within a reasonable compilation time

Keywords

circuit simulation; high level synthesis; integrated circuit modelling; low-power electronics; optimising compilers; EAC; architectural parameters; compilation time; cycle-accurate architectural-level energy simulator; energy consumption; energy models; energy-aware compilation framework; energy/performance constraints; error margin; estimation speedup; technological parameters; Analytical models; Assembly; Benchmark testing; Constraint optimization; Design optimization; Energy consumption; Optimizing compilers; Power generation; Signal processing; State estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Conference_Location

Paris

ISSN

1530-1591

Print_ISBN

0-7695-1471-5

Type

conf

DOI

10.1109/DATE.2002.998310

Filename

998310