DocumentCode :
379760
Title :
False path elimination in quasi-static scheduling
Author :
Arrigoni, G. ; Duchini, L. ; Lavagno, L. ; Passerone, C. ; Watanabe, Y.
Author_Institution :
Loquendo S.p.A., Torino, Italy
fYear :
2002
fDate :
2002
Firstpage :
964
Lastpage :
970
Abstract :
We have developed a technique to compute a Quasi Static Schedule of a concurrent specification for the software partition of an embedded system. Previous work did not take into account correlations among run-time values of variables, and therefore tried to find a schedule for all possible outcomes of conditional expressions. This is advantageous on one hand, because by abstracting data values one can find schedules in many cases for an originally undecidable problem. On the other hand it may lead to exploring false paths, i.e., paths that can never happen at run-time due to constraints on how the variables are updated. This affects the applicability of the approach, because it leads to an explosion in the running time and the memory requirements of the compile-time scheduler itself. Even worse, it also leads to an increase in the final code size of the generated software. In this paper we propose a semi-automatic algorithm to solve the problem of false paths: the designer identifies and tags critical expressions, and synchronization channels are automatically added to the specification to drive the search of a schedule
Keywords :
data flow computing; embedded systems; formal specification; processor scheduling; sequential machines; synchronisation; applicability; code size; compile-time scheduler; concurrent specification; critical expressions; embedded system; false path elimination; quasi-static scheduling; run-time values; running time; semi-automatic algorithm; software partition; synchronization channels; Algorithm design and analysis; Communication system control; Concurrent computing; Consumer electronics; Driver circuits; Embedded computing; Embedded system; Hardware; Processor scheduling; Runtime;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location :
Paris
ISSN :
1530-1591
Print_ISBN :
0-7695-1471-5
Type :
conf
DOI :
10.1109/DATE.2002.998416
Filename :
998416
Link To Document :
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