Title :
Statistical timing driven partitioning for VLSI circuits
Author :
Ababei, Cristinel ; Bazargan, Kia
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
Presents statistical-timing driven partitioning for performance optimization. We show that by using the concept of node criticality we can enhance the Fiduccia-Mattheyses (FM) partitioning algorithm to achieve, on average, around 20% improvements in terms of timing, among partitions with the same cut size. By incorporating mechanisms for timing optimization at the partitioning level, we facilitate wire-planning at high levels of the design process
Keywords :
VLSI; circuit layout CAD; circuit optimisation; high level synthesis; logic partitioning; network topology; statistical analysis; timing; wiring; Fiduccia-Mattheyses partitioning algorithm; VLSI circuits; cut size; high levels; node criticality; partitioning level; performance optimization; statistical timing driven partitioning; timing; wire-planning; Algorithm design and analysis; Circuits; Delay estimation; Design optimization; Partitioning algorithms; Process design; Process planning; Timing; Very large scale integration; Wire;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-1471-5
DOI :
10.1109/DATE.2002.998465
