Author_Institution :
University of Sevilla, Facultad de Fisica, Departamento de Electr?nica, Sevilla, Spain
Abstract :
The letter presents a multiprocessor system particularly advantageous in tightly coupled structures. The procedure is based on the fact that the microprocessor CPUs actually interact with the memory and I/O devices during a small fraction of the clock cycle. Conflicts in the memory bus access are avoided by a simple clocking and enabling method.
