Title :
Bringing test to design: testing in the designer´s event based environment
Author :
Rajsuman, Rochit
Author_Institution :
Advantest America R&D Center, Santa Clara, CA, USA
Abstract :
In this paper, we present a new tester that works in the IC designer´s simulation environment instead of traditional ATE test environment. The tester uses IC simulation data from a Verilog or VHDL simulator in the vcd format. The basic tester architecture and its operation are described.
Keywords :
automatic test equipment; circuit CAD; integrated circuit design; integrated circuit testing; ATE; EDA; IC design simulation; VCD format; VHDL; Verilog; tester architecture; Circuit simulation; Circuit testing; Computer architecture; Costs; Design engineering; Hardware design languages; Integrated circuit modeling; Integrated circuit testing; Signal design; Timing;
Conference_Titel :
Electronics Manufacturing Technology Symposium, 2002. IEMT 2002. 27th Annual IEEE/SEMI International
Print_ISBN :
0-7803-7301-4
DOI :
10.1109/IEMT.2002.1032781
